ggx: new instructions and porting the Linux kernel
The ggxdev MiBench harness is working pretty well now ("ant benchmark" will run them). I added my first new instructions based on benchmark results: inc and dec. Prior to inc and dec, you would often see code like this:
ldi.l $r1, 1
add.l $r0, $r1 # add 1 to $r0, and save result in $r0
This is a 8 byte sequence. We can drop that down to a single 2 byte instruction with the new "inc"rement instruction, which looks like this:
inc $r0, 1
It's encoded with a new 16-bit format that includes a single register operand and an unsigned 8-bit immediate value. Similarly, the dec instruction decrements a register by an 8-bit value. Teaching the compiler to use inc and dec was pretty easy. The MiBench results are now 8% smaller and 7% faster.
With the GCC test results looking good and GDB stumbling along better than before, now is the time to port the Linux kernel...
I started with the FR-V linux port because it has a uClinux implementation, and I have a passing familiarity with both the architecture and the kernel maintainer (hi David!). My basic strategy was to copy all of the FR-V bits over to new ggx directories, then hack and slash until it links. Anything I didn't understand I simply replaced with a stub that loops forever. This gets you to something that links very quickly, but doesn't boot very far. Then you simply fire up the kernel in gdb and tackle each hang until it starts to crawl. I also had to implement a Linux console that would talk to my simulator via the swi instruction, just as I had done in libgloss. This gives me IO to the gdb/sim console. So now....
$ ggx-elf-run vmlinux
Linux version 2.6.26 (green@spindazzle.org) (gcc version 4.4.0 20080827 (experimental) (GCC) ) #65 Wed Sep 10 06:02:38 PDT 2008
console [simcons0] enabled
Console: GDB GGX simulator stdio
uClinux GGX port by Anthony Green
Memory 00400000-00800000
Built 1 zonelists in Zone order, mobility grouping off. Total pages: 255
Kernel command line:
PID hash table entries: 16 (order: 4, 64 bytes)
...and then it hangs.
The ggx ISA so far only includes instructions you might use in a typical user-land program. The kernel, however, requires special support. The first thing I've hit is the need for some kind of program status word (PSW) to indicate if I'm in "user" mode or "supervisor" mode. I don't want to use any of my 16-registers for this. One idea is to map the PSW to a special memory location, but instead I've decided to add a new bank of registers to ggx, one of which will be the PSW register.
Earlier in this post I described a new instruction encoding for inc and dec that included a register operand and an 8-bit immediate value. I'm going to use this same encoding for the new instructions Get Special Register (gsr) and Set Special Register (ssr). The 8-bit value will identify one of 256 special registers that we can move in and out of the single register operand. I'll use special register 0 as the program status word. The other 255 registers will no doubt be handy for other system level things.
